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About

Table of Contents

Personal Introduction

I am a 4th-year CS undergraduate student at Beihang University. I am also an exchange student at University of Macau. I will be a first-year PhD student at University of Macau in August 2025, under the supervision of Prof. Huanle Xu.

Currently I am a research assistant in CDS Lab, advised by Prof. Huanle Xu on LLM inference system optimization and efficient scheduling. Before that, I was advised by Prof. Zhongzhi Luan on performance optimization and parallel computing.

Research Interests

My current research interests are broadly in the intersection between systems and machine learning, performance optimization and efficient scheduling of LLM systems for instance. For example, I am very interested in continuing work on research projects like Llumnix and LoongServe. At the same time, I am also very fascinated by the challenge of how to handle the deployment of new LLM optimization techniques into the system, such as the works done in PowerInfer, InfiniGen.

Projects

BattleByte: Online Programming Battle Platform

Github
  • Analyzed product requirements, designed in-game mechanics, authored product documentation and coordinated team efforts as a Product Manager.
  • Designed and developed the backend WebSocket real-time communication component.

Online Flea Market Platform

Github
  • Utilized the Flask framework to complete the backend code for user center and flea market functionalities.
  • Integrated the backend with databases using GaussDB for MYSQL and MYSQL.

Multi-threaded Elevator Scheduling System

Github
  • Developed a multi-threaded elevator scheduling system supporting elevator maintenance and elevator accessibility.
  • Developed a local greedy approach to handle the addition of elevators and maintenance requests.
  • Completed the development using the principles of object-oriented programming.

MIPS Pipeline Processor with Exception Handling Support

Github
  • Implemented a MIPS five-stage pipeline CPU that supports branch prediction and hazard handling.
  • Implemented external instruction memory and data memory.
  • Introduced CP0, Bridge, and Timer to support interrupt and exception handling.